Data resampler for data processing system for logically adjacent data samples
US5977994A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 1998 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Feb 19, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T5/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data resampler for a data processing system for logically adjacent data samples is provided. The data resampler includes a memory subsystem for storing samples to be rendered, a digital differential analyzer (DDA) for generating an interpolation corner address for a sample to be rendered and which also generates a set of interpolation fractions. The resampler also includes a fetch unit, which receives the generated interpolation corner address and generates four source addresses of samples to be fetched from the memory subsystem. A number of memory units are included in the resampler. The first memory unit is a first in, first out FIFO memory, for holding the generated interpolation fractions and for permitting the DDA and fetch unit to continue to operate during memory read latency periods. The second memory unit is also a FIFO memory and is used to hold pixel data. The resampler further includes an interpolation unit, which receives pixel data from the second FIFO memory unit and interpolation fractions from the first FIFO memory unit. The interpolation unit then computes rendered result pixels, assembles the result pixels into memory words and outputs the words to a destinatio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.