Synchronous read channel integrated circuit employing a channel quality circuit for calibration
US5978162A · kind A · utility
19Cited by
48References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1997 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Mar 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2020/1476
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. A Channel Quality circuit accumulates various signals generated by the read channel, such as sample errors, gain errors, timing errors, etc., for use in calibrating the read channel components and estimating the bit error rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.