Stacked-fringe integrated circuit capacitors
US5978206A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1997 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Sep 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A capacitor that is adapted for construction over a substrate in the metal interconnect layers provided by conventional integrated circuit processes. The capacitor includes a first conducting layer separated from the substrate by a first dielectric layer and a second conducting layer separated from the first conduction layer by a second dielectric layer. The second conducting layer is divided into a plurality of electrically isolated conductors in an ordered array. Every other one of the conductors is connected to a first terminal, and the remaining conductors are connected to a second terminal. The first conducting layer includes at least one conductor which is connected to the first terminal. In one embodiment of the invention, the first conducting layer also includes a plurality of electrically isolated conductors in an ordered array, every other one of the conductors being connected to the first terminal and the remaining conductors being connected the second terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.