Semiconductor non-volatile memory device and computer system using the same
US5978270A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1998 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Mar 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
After decreasing the threshold voltages of a plurality of memory cells collectively or selectively, the presence or absence of any memory cell of which the threshold voltage has dropped below a predetermined voltage verified collectively for each of memory cell groups connected to word line (low-threshold value verification), and any memory cell of which the threshold voltage has excessively dropped is selectively written. Also, the well of each of memory cell is formed in the region of an element isolation layer for isolating it from the substrate of a memory apparatus, and a negative voltage is supplied to the memory well distributively with a positive voltage applied as a word line voltage, thus supplying them as erase operation voltages. The absolute value of the memory well voltage is set substantially equal to or lower than the word line voltage for the read operation. Sectors constituting each memory mat includes a sector (selected sector) selected for the erase operation with each word line thereof supplied with a positive voltage, a sector (non-selected sector) not selected for the erase operation with a word line voltage different from a memory well voltage, and further a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.