Electrically erasable nonvolatile memory
US5978276A · kind A · utility
21Cited by
8References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 20, 1998 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Aug 20, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory cell which is highly scalable includes a cell formed in a triple wall. The control gate is negatively biased. By biasing the P-well and drain (or source) positively within a particular voltage range when erasing, GIDL current and degradation from a hole trapping can be diminished and hence scalable technology may be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.