Distributed pre-fetch buffer for multiple DMA channel device
US5978866A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 16, 1997 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | May 16, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Higher speed data transactions between a host computer's system memory and a plurality of slow peripheral devices are accomplished by providing distributed DMA functions along with distributed pre-fetch buffers. The first I/O device accesses the host bus via a first DMA channel and a first pre-fetch buffer, the second I/O device accesses the host bus via a second DMA channel and a second pre-fetch buffer, and the third I/O device accesses the host bus via a third DMA channel and a third pre-fetch buffer. In a first DMA transaction, the first pre-fetch buffer is filled with data being transferred between the first I/O device and the host system memory. While the data are transferred between the pre-fetch buffer and either the first I/O device or the system memory, the second pre-fetch buffer is being filled pursuant to a second DMA transaction between the second I/O device and the system memory. This strategy increases the speed of successive DMA transactions between a plurality of I/O devices and the host computer system's memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.