On-chip parallel-serial data packet converter to interconnect parallel bus of integrated circuit chip with external device
US5978870A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 1997 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Oct 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed a single chip integrated circuit device having a bus system, functional circuitry, and external port, and a parallel/serial data packet converter interconnecting the bus system and the external port. The parallel/serial data packet converter is operable to convert parallel data from the bus system into bit serial packets for output through the port, and allocate a packet identifier to the bit serial packets in dependence on the information received from the bus system in accordance with a predetermined protocol. A method of effecting communication between a single chip integrated circuit device and an external device using such a parallel/serial data packet converter is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.