Method and system for increased instruction dispatch efficiency in a superscalar processor system
US5978896A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1994 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Aug 12, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit for dispatching instructions from an associated instruction buffer to multiple execution units on an opportunistic basis. The dispatch status of instructions within the associated instruction buffer is periodically determined and, in response to a dispatch of the instructions at the beginning of the instruction buffer, the remaining instructions are shifted within the instruction buffer in the application specified sequential order and a partial group of instructions are loaded into the instruction buffer from the instruction queue utilizing a selectively controlled multiplex circuit. In this manner additional instructions may be dispatched to available execution units without requiring a previous group of instructions to be dispatched completely.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.