System for improving processing efficiency in a pipeline by delaying a clock signal to a program counter and an instruction memory behind a system clock
US5978925A · kind A · utility
4Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 1997 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Nov 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a pipelined processor, when a conditional branch is effected in accordance with a state of calculation generated by immediately previous instruction, it is necessary for a conventional technique to insert a NOP (no operation) instruction before a conditional branch instruction. This lowers the processing efficiency. In order to solve this problem, a delay circuit generates a clock signal .phi.' which is supplied to a program counter and an instruction memory. The clock signal .phi.' is delayed behind a system clock .phi.. This obviates the need to insert such a NOP instruction and the processing efficiency is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.