Fault isolation feature for an I/O or system bus
US5978938A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1996 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Nov 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system including a bus connected to a plurality of devices capable of driving said bus, error reporting and isolation is achieved by signaling a self-check to each device connected to the bus to determine if it was driving the bus at the time an error occurred. The bus check request is generated by one of the devices connected to the bus in response to detecting either a parity error or an internal error. If a parity error is detected, a bus check request is signaled to a combining unit connected to the bus. The combining unit signals the self-check to each of the devices attached to the bus in response to receiving the bus check request. Each device determines whether it was driving the bus at the time the error occurred and, if so, sets a source of error indicator on the device. Similarly, if an internal error is detected, the detecting device sets source of error and internal error indicators on the detecting device and signals a bus check request to the combining unit. The source of error and internal error indicators are accessible to a machine check or service processor mechanism in the data processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.