Self-alignment process usable in microelectronics, and application to creating a focusing grid for micropoint flat screens
US5981304A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1997 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Dec 17, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J9/025
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Self-alignment process usable in microelectronics to obtain alignment of at least one group of holes, one of said holes (or large diameter hole) being formed in an upper level and the other hole (or small diameter hole) being formed in a lower level of a stacked structure. The process consists of: PA1 providing a conducting layer in the structure, said conducting layer possibly being connected to an external electrical circuit, PA1 disposing an insulating layer on said conducting layer, PA1 piercing the insulating layer with a hole of said small diameter that penetrates as far as the conducting layer, PA1 carrying out an electrolytic deposit of a conducting material in the small diameter hole using the conducting layer as the electrode during the electrolysis procedure, said electrolytic deposit filling the small diameter hole from the conducting layer and causing the deposit to overflow onto said insulating layer to give the electrolytically deposited conducting material the shape of a mushroom whose head rests on said insulating layer, the electrolytic deposition being continued until the diameter of the mushroom head attains the size of the large diameter, PA1 depositing on the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.