Semiconductor memory device having improved stacked capacitor cells
US5981989A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 1994 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Sep 26, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
The invention provides a stacked capacitor cell structure for a semiconductor memory device. The cell includes a transistor formed in an active region in a surface of a semiconductor substrate; a first inter-layer insulator both overlying the transistor and having a contact hole over the transistor; a second inter-layer insulator both overlying the first inter-layer insulator and having a through hole with a larger diameter than the diameter of the contact hole; a stacked capacitor both formed within the through hole formed in the second inter-layer insulator and comprising a storage electrode electrically connected to the transistor through the contact hole, a capacitive insulation film and an opposite electrode; and a third inter-insulator overlying both the stacked capacitor and the second inter-layer insulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.