Clock multiplier having two feedback loops
US5982208A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 1998 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Jan 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock multiplier controls the frequency of an output clock signal according to the frequency of an input clock signal by means of two feedback loops. The first feedback loop, active during a fixed number of initial cycles of the input clock signal, counts cycles of the output clock signal during each cycle of the input clock signal, and controls the output clock frequency according to the resulting count values. The second feedback loop, used after the fixed number of initial cycles, divides the frequency of the output clock signal, and controls the output clock frequency according to the phase difference between the resulting divided signal and the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.