Phase locked loop circuit and a picture reproducing device
US5982239A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Feb 9, 1998 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Feb 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A first phase comparator 22 of digital type and a second phase comparator 32 of sampling type are provided. Near a lock phase, an output current Iout2 is fed from the second phase comparator 32 to a voltage-controlled oscillator 14 through a change-over switch 40. In other phases, an output current Iout1 is fed thereto from the first phase comparator 22. When a reference signal fs is missing, a complementing circuit 50 complements a pulse to at least the reference signal fs input to the first phase comparator 22. A noise detecting/removing circuit 60 detects and removes noise from the reference signals fs, permits the reference signals fs to be fed to the first and second phase comparators 22 and 23, and halts the operations of the two phase comparators 22 and 32 for only a predetermined period of time after the noise has been detected. Therefore, the PLL circuit stably operates and characters are clearly displayed on a screen even when the noise is contained in the horizontal synchronizing signals of the video signals or even when the signals are missing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.