Parallel-to-serial CMOS data converter with a selectable bit width mode D flip-flop M matrix
US5982309A · kind A · utility
67Cited by
9References
29Claims
0Family size
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Key dates
| Filing date | Jan 9, 1998 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Jan 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed parallel-to-serial CMOS data transmitter uses a D Flip-flop matrix architecture to combine a shift scheme with a selection scheme to serialize parallel bit data. Data is partially serialized through multi data paths at a much lower frequency and a time-division multiplex scheme selects one bit from each data path allowing for pipelined data processing. The CMOS architecture uses selective load clock mode switching allowing different word bit widths to be processed simply by adjusting the frequency of a loading clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.