Flash memory cell array and method of programming, erasing and reading the same
US5982671A · kind A · utility
9Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 24, 1997 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Dec 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a flash memory array in which four memory cells formed on a silicon substrate having a double well structure hold a source region or a drain region in common so that the area occupied by contact holes can be minimized and integration of device can be enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.