Method and apparatus for monitoring frequency synthesizer locking time
US5982812A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 1997 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | May 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0016
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A frequency synthesizer circuit comprises a controller, a synthesizer and a voltage controlled oscillator are used to generate an oscillating signal in response to external commands. The synthesizer provides a lock detect signal to the controller when the synthesizer detects that the oscillating signal has reached a desired frequency following application of a load signal. A first timer, a second timer, and a counter are adapted to receive the load signal and the lock detect signal. The first timer provides a first measurement corresponding to an amount of time between the load signal and a first receipt of the lock detect signal. The second timer provides a second measurement corresponding to an amount of time between the load signal and a final receipt of the lock detect signal. The counter provides a count value corresponding to a total number of times that the lock detect signal is received inclusive of the first receipt and the final receipt of the lock detect signal. A memory device is coupled to each of the first timer, second timer, and counter, which has a data storage portion for storing the first measurement, second measurement and count value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.