Power down system and method for pipelined logic functions
US5983339A · kind A · utility
24Cited by
15References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 21, 1995 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Aug 21, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Logic circuitry added to each stage of a pipeline of staged logic circuitry sequentially removes a clock signal from each stage when data incoming to the pipeline is invalid, or not to be processed for any practical use. The same logic circuitry is also useful for reapplying the clock signal to the successive stages of the pipeline when valid data is to be processed by the pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.