Power conservation method and apparatus activated by detecting shadowed interrupt signals indicative of system inactivity and excluding prefetched signals
US5983356A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1996 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Jun 18, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is disclosed for controlling the application of a clock stopping signal in a processor to limit power consumption. The system controller receives addresses, signals indicative of primary and secondary system activity, and at least one nap timeout signal. Interrupt addresses or programmed addresses are trapped and stored as shadowed addresses. Current addresses may be compared with shadowed addresses. Matching addresses trigger a nap mode. Upon nap mode triggering, the clock stopping signal may be applied during a throttling period. Applying the clock stopping signal with programmable duty cycle during the throttling period ensures that processing necessary for the detection and servicing of primary and secondary activity can occur. A prefetch detect circuit ensures that shadowed addresses loaded in the middle of a prefetch do not trigger the clock stopping signal. Clock stopping signal is removed or inhibited when primary or secondary activity is detected or when a nap timer expires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.