Processor fault recovering method for information processing system
US5983359A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1997 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Mar 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault recovering method for substituting an instruction processor (IP) for a system supporting processor to execute processing thereof when the system supporting processor fails. An apparatus implementing this processing method comprises a plurality of processors, at least one of which is operated as a system supporting processor (SSP) and the rest of which are operated as instruction processors. When the SSP fails, an interrupt is generated to an OS running on at least one IP. The OS recognizes that a fault occurred in the IP, abnormally terminates an application program which has been running on the IP when the interrupt was generated, or stops instruction processing as the IP falling into a hardware failure state, or input a command for disconnecting an alternate instruction processor for the system supporting processor, so that the IP takes over functions of the SSP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.