Microprocessor having a CPU and at least two memory cell arrays on the same semiconductor chip, including a shared sense amplifier
US5983367A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1997 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Apr 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CPU can selectively execute a normal processing mode and a debugging mode on the basis of a control signal sent from a control unit. A first memory cell array is accessed in the normal processing mode, and a second memory cell array is accessed in the debugging mode. A sense amplifier and a bit line are shared by the first and second memory cell arrays. Consequently, it is possible to relieve an increase in the area of the semiconductor chip caused by existence of the two memory cell arrays. That is, an area of a semiconductor chip is reduced. A spare memory cell array may be provided for compensating for a defective cell of the first memory cell array. A refresh circuit may be provided for refreshing the first and second memory cell arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.