Voltage level translation for an output driver system with a bias generator
US5986472A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1997 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Jun 6, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuit and method aspects are provided for voltage level translation circuit for an output driver. In a circuit aspect, a circuit includes an input mechanism for receiving an internal data signal of a first predetermined voltage range, at least two stacked transistors coupled to the input mechanism, and a bias generator coupled to the input mechanism and the at least two stacked transistors, the bias generator ensuring that the at least two stacked transistors operate below a predetermined maximum device voltage. The circuit further includes an output mechanism coupled to the at least two stacked transistors, the output mechanism providing an external signal of a second predetermined voltage range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.