Chip attenuator having a capacitor therein
US5986516A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 1997 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Dec 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H7/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An attenuator includes a flat, substantially rectangular substrate of an insulating material having a surface. A plurality of termination areas of a conductive material are on the substrate surface and are spaced from each other. Three resistors are on the substrate surface and are connected in a series parallel combination between the termination areas. The resistors may be formed by three separate resistance layers extending between and connected to the termination areas, or a single resistance layer extending between and connected to the termination areas. A shunt capacitor is on the substrate surface and is connected to one of the resistors. The shunt capacitor is formed by an area of a conductive material on the substrate surface and overlapping a portion of the resistors, and a dielectric layer between the conductive area and the resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.