Read/write channel write precompensation system and method using one or more delay clocks
US5986830A · kind A · utility
89Cited by
19References
20Claims
0Family size
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Key dates
| Filing date | Jul 30, 1997 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Jul 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B5/012
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An improved write precompensation circuit for a read/write channel circuit and system is provided. Multiple data input signals are provided, each being clocked by a different clock. The data input signals are then multiplexed. Two, three or more data clock delays may be utilized to provide two, three or more data delays to achieve the write precompensation. Only one edge of a signal need pass through a multiplexer before the multiplexer may change state. The amount of delay may be user programmable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.