Clock circuit for the reading of sequentially recorded information elements in a multitrack recording system
US5986834A · kind A · utility
8Cited by
20References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A clock circuit for the reading of sequential information elements includes a phase-locked loop for the control of the controlled oscillator. In the case of a reading system with n tracks, the phase computation circuit, the digital filter and the controlled oscillator each include as many memories (delay circuits R 1.1, . . . R 2.1, . . . R 3.1, . . . ) as there are samples of information elements (or information tracks) to be processed almost simultaneously. The invention finds particular application in the reading of high-density recording media.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.