Semiconductor memory device having variable number of selected cell pages and subcell arrays
US5986933A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1997 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Nov 21, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device for easily optimizing a page size and a block size according to use in order to perform write, read and erase operations at the same time is provided. If a user inputs a command from outside using a memory device having a plurality of standard sub-cell arrays or if a short process step is added to memory devices at the time of their shipping, the page sizes for the read and write operations can freely be selected, and the write, read and erase units can be optimized according to use in a system design, therefore, the highest system performance can be achieved, and an advantage in compatibility of devices of different generations can be obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.