Semiconductor memory device
US5986942A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 1999 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Jan 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device (100) having reduced logic gates for selecting sense amplifier columns (102-0 to 102-2) is disclosed. Sense amplifier columns (102-0 to 102-2) are selected according to block address values X5 to X0. The order in which sense amplifier columns (102-0 to 102-2) are selected corresponds to a gray code in the lower two significant block address values (X1 and X0). In this arrangement, X1 can be applied to a NAND gate 110-0 within sense amplifier selecting circuit 106-1 as predecoded signal C1. X0 can be applied to a NAND gate 110-1 within sense amplifier selecting circuit 106-2 as predecoded signal C2. The use of predecoded values (X0 and X1) instead of decoded values can reduce the logic required to select the sense amplifier columns (102-0 to 102-2).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.