Matrix processor
US5987488A · kind A · utility
7Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1997 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Dec 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A matrix computation processor comprises a control unit and a data memory, and a plurality of computation units. The plurality of computation units are controlled by the control unit by means of a control bus comprising: a first group of wires connected to the plurality of computation units conveying a common instruction to the plurality of computation units; and a plurality of second groups of at least one wire, each being connected respectively to one of the plurality of computation units, conveying an instruction complement specific to each computation unit of the plurality of computation units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.