Modular arithmetic coprocessor enabling the performance of non-modular operations at high speed
US5987489A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 26, 1997 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Feb 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/728
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a device including three registers, one input terminal to receive pieces of binary data to be stored in these registers, a multiplication circuit enabling the performance of a multiplication operation between two pieces of data stored in two of the registers, a first addition circuit enabling the performance of an addition operation between a piece of data stored in the second register and a piece of data produced by the multiplication circuit, a subtraction circuit placed between the second register and the addition circuit, a delay cell and a second addition circuit placed between the first addition circuit and the input of the second register, multiplexing circuitry making it possible to provide the contents of the second register or a permanent logic state to one input of one of the addition circuits, to connect another input of the addition circuit to an output of the multiplication circuit and to connect an output of the addition circuit to an input of the second register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.