Mac processor with efficient Viterbi ACS operation and automatic traceback store
US5987490A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1997 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Nov 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6569
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dual-MAC processor optimized so that two Viterbi ACS operations, including traceback bit storage, can be executed in two machine cycles is disclosed. The processor comprises a pair of adder arithmetic logic units connected to a common accumulator register bank and supporting full and split-mode add, subtract, and compare operations. Viterbi compare operations are executed using the subtract function and the sign bit is combined with a compare mode bit to generate a traceback output which indicates the proper traceback bit to store. When a compare operation is performed and a Viterbi mode bit is active, each generated traceback output is shifted into a traceback register for later use in a Viterbi traceback routine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.