Data processor with protected non-maskable interrupt
US5987559A · kind A · utility
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9References
5Claims
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Key dates
| Filing date | Feb 2, 1998 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Feb 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt scheme for a data processor includes an enable field for a non-maskable interrupt (NMI). The field is automatically cleared by the data processor when it services the highest priority interrupt, a RESET. The user can set the field to enable a subsequent NMI but cannot himself clear the NMI. This strategy prevents an NMI from interrupting a RESET service routine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.