Apparatus for executing coded dependent instructions having variable latencies
US5987594A · kind A · utility
47Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1997 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Jun 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor that executes coded instructions using an instruction scheduling unit receiving the coded instructions and issuing an instruction for execution. A replay signaling device generates a signal indicating when the instruction failed to execute properly within a predetermined time. A replay device within the instruction scheduling unit responsive to the signaling device then reissues the instruction for execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.