Chip scale package type of semiconductor device
US5990546A · kind A · utility
129Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1995 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Dec 29, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device in which the space between a semiconductor chip and an auxiliary wiring plate is sealed with resin. The auxiliary wiring plate has insulating layers and on both sides of the routing conductor, the insulating layer on the side of the semiconductor chip has a hole being led from the routing conductor to the electrode of the semiconductor chip, the metal filled in the hole and the metal bump formed so as to protrude from the hole serves as an inner electrode. The semiconductor device can be manufactured by the TAB technique.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.