CMOS I/O circuit with high-voltage input tolerance
US5990705A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 4, 1997 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Jun 4, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention provides for an input/output circuit in a CMOS integrated circuit which can withstand pad voltages which are higher than the supply voltages for the integrated circuit. The input/output circuit has a pair of first polarity-type transistors which is connected in series between a first supply voltage terminal and the input/output pad, and a pair of second polarity-type transistors which is connected in series between a second supply voltage terminal and the pad. Responsive to a disable control signal, one of the first polarity-type and one of the second polarity-type transistors are turned off. Switch circuitry is connected between the pad and a gate of a second transistor of the second polarity-type transistor pair. The switch circuitry forms an open circuit when the pad voltage is in the range of the supply voltages of the input/output circuit, and forms a closed circuit to connect the gate to the pad when the pad voltage is outside the range of supply voltages so that no conducting path is created through the pair of second polarity-type transistors. This allows the pad to remain in a high impedance state even when the pad voltage is outside the range of supply volta…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.