Method and system for sliced integration of flash analog to digital converters in read channel circuits
US5990707A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 1997 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Sep 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method is provided having a flash analog-to-digital converter (ADC) that includes an input signal buffer, a plurality of identical voltage comparators, and a reference generator. A clock signal defines the time instances at which the instantaneous input signal voltage is compared against a plurality of reference voltages generated by the reference generator. The individual comparator consists of a an integrating amplifier stage followed by an analog latching stage and a digital latch. The integrating amplifier input is allowed to track the input signal continuously. The amplifier output voltage is forced to a voltage close to zero before each conversion cycle is initiated by the ADC clock. At the beginning of the conversion cycle, the amplifier output is released and its voltage will follow an excursion related to the integral of the input of the amplifier. At a predefined time moment later, the analog latch is activated. When activated, the analog latch performs a binary decision that exclusively depends on the sign of the amplifier output voltage at the moment of the an analog latch is activation. The analog latch output may be synchronized with the ADC clock with a …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.