Adaptive filtering scheme for sampling phase relations of clock networks
US5990719A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1997 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Oct 7, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for adjusting phase relation of a plurality of clock signals in a processor. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates a first output based on a phase relation between those clock signals. A controller then adjusts the delay of the clock signals based on the first output of the phase detection circuit and a bit of a delay shift register to synchronize the clock signals within a predefined range. The controller generates a second output if the phase relation between the plurality of clock signals has changed before the adjusting of the delay of the clock signals has occurred. A noise band circuit is configured to receive the second output of the controller and adjust the predefined range in response to the receiving of the second output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.