High-speed synchronous clock generated by standing wave
US5990721A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 1997 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Aug 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock for digital devices. Ordinarily, when multiple digital devices are clocked by a common clock, the clock signals frequently arrive at the digital devices at different times, due to propagation delays. The devices are thus not clocked synchronously. Under the invention, the multiple devices are connected to a common transmission line. A standing wave is generated on the transmission line, and the periodic collapse of the standing wave is used to clock the devices. Synchronous clocking to within about 1.0 nano-seconds has been attained, in a transmission line about ten feet long, wherein a clock signal ordinarily takes about 15 nanoseconds to travel from one end to the other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.