Delay line ramp demodulator
US5990733A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 1998 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Feb 19, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D3/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a demodulator having delay circuitry and demodulation control circuitry that may be fully formed within a common integrated circuit. The delay circuitry receives an input signal and generates a delayed input signal. The demodulation control circuitry generates a demodulated output based upon the input signal and the delayed input signal that has a level that is proportional to, or a finction of, a period of a respective cycle of the input signal. The demodulation control circuitry includes pulse generation circuitry, pulse delay circuitry, pulse conversion circuitry and sampling circuitry. The pulse generation circuitry generates a signal pulse based upon the input signal and the delayed input signal with a duration that is proportional to at least one period of the input signal. The pulse delay circuitry generates a delayed signal pulse based upon the signal pulse. The pulse conversion circuitry generates a converted signal that has a level based upon the duration of the signal pulse. The sampling circuitry samples the converted signal based upon a sample pulse to generate the demodulated output based upon the level of the converted signal. The delay…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.