Method and circuit for calibration of flash analog to digital converters
US5990814A · kind A · utility
46Cited by
24References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 5, 1997 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Sep 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for correcting comparator offsets which occur during operating conditions such that static and dynamic offsets are compensated is provided. The comparator may be calibrated for normal operating conditions. The calibration may be accomplished by providing adjustability of the comparators' threshold value and providing a feedback loop for adjusting the threshold value. In one preferred embodiment, the comparator may be utilized within a flash ADC, and in a more preferred embodiment, the comparator may be utilized within a flash ADC of a read/write channel circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.