Split sense amplifier and staging buffer for wide memory architecture
US5991209A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 11, 1997 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Apr 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an amplifier design for a wide memory architecture, a staging buffer can be integrated with the final stage of a multi-stage sense amplifier. The staging buffer includes a memory latch for storing at least one bit of data. The data is transferred into the staging buffer from memory upon strobing at least one read enable line, and transferred from the staging buffer to a data bus upon strobing at least one write enable line. The data signal is transferred from the memory to the staging buffer at a voltage level lower than the full swing voltage level. The memory architecture produced using this design technique allows for a much lower voltage swing on all of the data lines, thus lowering the power requirements of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.