Semiconductor memory device with redundancy control circuits
US5991211A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1998 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Oct 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device has sets of address fuses which are arranged in a plurality of fuse rows in order to provide a larger number of redundant elements. The sets of address fuses are associated with addresses, respectively, and at least one address fuse included in each of the sets of the address fuses is provided in only one of the fuse rows. Address buses are provided such that the number of address lines associated with the sets of the address fuses is less than the number of fuse rows. One of the address lines is located closer to one of the fuse rows which includes associated address fuses than a center line between the one of the fuse rows and another one of the fuse rows which is adjacent to the one of the fuse rows is. The address lines are connected to redundant element control circuits through local lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.