Method and apparatus for split-brain avoidance in a multi-processor system
US5991518A · kind A · utility
47Cited by
6References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1997 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Jan 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0757
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A split brain avoidance protocol to determine the group of processors that will survive a complete partitioning (disconnection) in the inter-processor communications paths connecting processors in a multi-processor system. Processors embodying the invention detect that the set of processors with which they can communicate has changed. They then choose either to halt or to continue operations, guided by the goal of minimizing the possibility that multiple disconnected groups of processors continue to operate as independent systems, each group having determined (incorrectly) that the processors of the other groups have failed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.