Verification support system
US5991533A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 1997 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Oct 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A verification support system having the following characteristics: (1) Before actually making a CPU mounted circuit, virtually make a CPU mounted circuit model and an ICE model and perform verification of the CPU mounted circuit mode with logic simulation, by using the ICE model; (2) When an error is found in the verification of a program using logic simulation, the execution and verification of the steps up to one step before the error point is omitted and execution and verification are performed immediately from the error point, for the purpose of error correction; (3) A waveform obtained as a result of logic simulation and a partially enlarged waveform thereof are displayed on different display regions; (4) A display region for displaying a waveform obtained as a result of logic simulation every hour and a display region for saving a displayed waveform obtained when logic simulation is stopped, are provided separately; (5) When there are a plurality of target logic models, waveforms of logic simulation results are displayed on different display regions, respectively. The stop or restart of the renewing of waveforms can be performed individually or collectively; (6) Before makin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.