Method and system for generating a program to facilitate rearrangement of address bits among addresses in a massively parallel processor system
US5991866A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1994 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Jun 7, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17381
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for generating a program to enable reassignment of data items among processors in a massively-parallel computer to effect a predetermined rearrangement of address bits. The computer has a plurality of processing elements, each including a memory. Each memory includes a plurality of storage locations for storing a data item, each storage location within the computer being identified by an address, comprising a plurality of address bits having a global portion comprising a processing element identification portion and a local portion identifying the storage location within the memory of the particular processing element. The system generates a program to facilitate use of a predetermined set of tools to effect a reassignment of data items among processing elements and storage location to, in turn, effect a predetermined rearrangement of address bits. The system includes a global processing portion and a local processing portion. The global processing portion generates a global program portion to enable use of the tools to effect a reassignment of data items as among said processing elements to, in turn, effect a rearrangement of the global portion of said address …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.