Processor
US5991872A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1997 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Oct 9, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Microprocessors use a conditional branch instruction so as to change processing in accordance with conditions. According to the prior art, a NOP instruction, which causes no operation, is used when a condition is satisfied, and the use of the NOP instruction inevitably lengthens the processing time. According to the present invention, a conditional transfer instruction is included in the instruction set of a microprocessor, and a flag decoder is additionally employed. The flag decoder determines whether a condition is satisfied or not, and outputs a control signal on the basis of the determination. The control signal is supplied to the instruction decoder of the processor to make a data transfer operation effective or ineffective. Accordingly, it is not necessary to use a NOP instruction, and the processing time can be as short as possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.