Semiconductor integrated circuit device and its test method
US5991906A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 20, 1998 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Jan 20, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318527
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a semiconductor integrated circuit device having a test circuit, the test time can be shortened and further the circuit activation ratio can be increased, while reducing the circuit scale. In the operation test mode, the counter circuit (10) is divided into the first counter circuit (10a) and the second counter circuit (10b) by use of the test circuit (20). Further, the same input count clock CK is inputted at the same time to both the first and second counter circuits (10a, 10b) in parallel. The normal operation of the counter circuit (10) can be discriminated by checking whether the output signal A of the first counter circuit (10a) matches the output signal B of the second counter circuit (10b) or not.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.