Method of making SRAM having part of load resistance layer functions as power supply line
US5994180A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 1997 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Aug 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/15
Abstract
In a method of manufacturing a static memory device, a patterning process is performed to a lamination film composed of a first insulating layer, a first conductive layer, a second insulating layer and a second conductive layer with regions for load resistors. A lamination section of the first insulating layer and the first conductive layer are separated through the first and second patterning processes into first to fourth portions. The first and second portions respectively functioning as parts of the word line which are connected to each other and as the gates of the transfer MOS transistors, and the third and fourth portions respectively functioning as gates of the drive MOS transistors. The second conductive layer is separated through the second patterning process into fifth and sixth portions, and the fifth and sixth portions respectively functioning as parts of the power supply line which are connected to each other and as the load resistors connected to the parts of the power supply line. The fifth and sixth portions are laminated on a set of the first and third portions and a set of the second and fourth portions via the second insulating layer, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.