Semiconductor device with impurity layer as channel stopper immediately under silicon oxide film
US5994190A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 10, 1998 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Sep 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first conductivity type low concentration impurity layer provided around a thick silicon oxide film, which is formed for element isolation in a first conductivity type element region as a surface region in a semiconductor substrate, and a second conductivity type impurity layer which is provided immediately under at least the thick silicon oxide film. The second conductivity type impurity layer constitutes a channel stopper to enhance the effect of element isolation. The first conductivity type low concentration impurity layer has an effect of improving the P-N junction breakdown voltage of an active region in the first conductivity type element region, and suppresses the narrow channel effect of a MOS transistor in the first conductivity type element region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.