Fabrication process for a semiconductor device
US5994214A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 1997 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Jan 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An upper wiring layer formed with a bonding pad portion has a stacked structure of a first titanium nitride film, a titanium film, a second titanium nitride film and an aluminum alloy film on the upper surface of an interlayer insulation layer. Also, the upper wiring has a stacked structure of titanium silicide film, the titanium film, the titanium nitride film and the aluminum alloy film. The fabrication process includes forming the interlayer insulation layer having a silicon oxide film by plasma CVD using silane and N.sub.2 O and processing an upper surface of the interlayer insulation layer by plasma under a nitrogen atmosphere to form a plasma processed nitrogen layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.