Field effect transistor array including refractory metal silicide interconnection layer
US5994726A · kind A · utility
18Cited by
3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1997 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Oct 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/90
Abstract
Connection between a PMOS transistor and an NMOS transistor is made through a refractory metal salicide layer in the source and drain regions of these transistors. The salicide is low in resistance, thereby partially substituting for a first Al wiring in intracell wiring. The resulting empty area provides a wiring area and, hence, the freedom of chip layout is enhanced. Besides, in a microcell which constitutes a logic circuit, such as a gate array, lateral wiring grid dots can be utilized as a wiring area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.